Feb 15, 2025 | Posted by Abdul-Rahman Oladimeji
Synopsys has expanded its Hardware-Assisted Verification (HAV) portfolio to support advanced semiconductor design. The updates include adding HAPS-200 prototyping and ZeBu-200 emulation systems to its product line and enhancing its ZeBu Server 5 to support scalability beyond 60 billion gates to address the growing hardware and software complexity in SoC and multi-die design
Frank Schirrmeister, executive director of Synopsys product management and markets group, said there are four trends driving the company’s hardware-assisted verification efforts: Software complexity, hardware complexity, and interface and architectural complexity.
Frank Schirrmeister, executive director of Synopsys product management and markets group, said there are four trends driving the company’s hardware-assisted verification efforts: Software complexity, hardware complexity, and interface and architectural complexity.
“In order to verify all [these four elements], you need to do a quadrillion cycles and what the means is verification is happening in phases – there’s verification at the IP core level, then you build subsystems… then you build full SoCs again with software stacks on top, and then you go all the way to the multi-die,” he said. “So Hardware-Assisted Verification is the bridging of the gap between the early verification and the full system verification.”
The four key components to addressing these challenges are performance, speed, scalability – you need to be able to address various types of designs – and ROI.
The HAPS-200 prototyping system offers “industry-leading runtime performance” and faster compile, with 4x improved debug performance when compared to the HAPS-100. It also uses the existing HAPS-100 ecosystem and supports mixed HAPS-200/100 system setups, scalable from single FPGA to multi-rack setups with capacity of up to 10.8 billion gates.